89
Anexo B
Artigo apresentado no Congresso EUROSOI 2007 em Louvain – Bélgica para o Estudo de
Ruído Flicker em OTAs Convencional e GC SOI nMOSFET.
Flicker Noise Analysis in CMOS OTA Using Fully
Depleted Graded-Channel SOI nMOSFET
Salvador Pinillos Gimenez
1,2
, Rogerio Laureano Gomes
1
and Marcelo Antonio Pavanello
1,2
1
Centro Universitário da FEI,
Av. Humberto de Alencar Castelo Branco, no 3972, 09850-901, São Bernardo do Campo, Brazil, sgimenez@fei.edu.br
2
Laboratório de Sistemas Integráveis,
Escola Politécnica da U. de São Paulo, Av. Prof. Luciano Gualberto, trav. 3, 158, 05508-900, São Paulo, Brazil
Abstract
This paper performs a flicker noise comparative study in
CMOS OTAs implemented with conventional and
Graded Channel (GC) SOI nMOSFETs based on SPICE
simulations. Two design targets are taken into account
fixing die area and transconductance to drain current
ratio. It is verified that GC OTAs present similar flicker
noise spectral density than those implemented with
conventional one with the same effective channel length
leading to an important die area reduction up to 27 %
while keeping similar performance.
1. Introduction
The use of GC SOI nMOSFET in analog and RF
applications is clearly established as reported in the
literature [1]. In saturation, the effective channel length
(L
eff
) can be approximated by the highy doped region
length (L
HD
) (L
eff
=L
HD
=L-L
LD
, L
LD
being the length of
lightly doped region) [1]. Reference [2] performed a
comparative study between the high gain (HG) and high
frequency (HF) single-stage OTAs implemented with
conventional (conventional OTA) and GC SOI
nMOSFETs (GC OTA), based in experimental results
and SPICE simulations, concluding that OTAs
implemented with GC SOI present improved open-loop
voltage gain (A
V0
), without degrading the unity-gain
frequency (f
T
), phase margin (PM) and slew rate (SR),
with an expressive die area reduction, depending on the
L
LD
/L ratio used. Reference [3] shows that input-
referred flicker noise spectral density (S
VG
) of GC SOI
with different L
LD
/L is higher than conventional SOI at
10 Hz, in saturation region, regarding fixed the mask
channel length of 3 µm. The goal of this paper is to
perform a comparative study between CMOS OTAs
implemented with conventional and GC SOI
nMOSFETs in order to verify the flicker (1/f) noise. The
base for comparison bas been the OTA design
developed in reference [4] for conventional SOI
transistor, whereas only the nMOSFET devices are
replaced by GC SOI with L
LD
/L ratio equal to 0.33. Two
different design targets (DT) are taken in account, the
first one with similar die area (DTI) and the second with
fixed g
m
/I
DS
(DTII). Both DT have same power
dissipation, by fixing the differential pair drain current
(I
DS
). In DTI, the die area is maintained constant by
fixing the mask channel length (L) of conventional and
GC SOI nMOSFETs. In this situation the g
m
/I
DS
is
different because the conventional SOI L
eff
are higher
than GC SOI nMOSFET (L
HD
). In DT II, g
m
/I
DS
is fixed
by GC SOI nMOSFETs channel length (L
HD
) increase,
in order to reach the same conventional SOI nMOSFET
L
eff
, resulting GC OTA with larger die area.
2. SPICE BSIM3SOI Models Calibration
Table 1 presents the dimensions (W/L), in micrometers,
of each transistor used in the implementation of
conventional and GC OTAs, used to perform the SPICE
BSIM3SOI v. 3.1 [5] flicker noise (1/f) comparison
study.
Table I: W/L ratios of transistor used in conventional and GC
OTAs for DT I an II.
HF OTA 1 2 3 4
L
LD
/L
- 0.33 0.33 0.33
M1-M2
600/3
600/3 600/4.5 400/4.5
M3-M4
300/6 300/6 300/6 300/6
M5-M6
300/6 300/6 300/6 300/6
M7-M8
200/5
200/5 200/7.5 134/7.5
M9-M10
600/3
600/3 600/4.5 400/4.5
Note: The shaded cells regard GC SOI nMOSFETs W/L ratios
As proposed in ref. [6], the series association of two
conventional SOI nMOSFETs is used to represent the
GC SOI nMOSFET. Each conventional SOI nMOSFET
represents one channel part, with its respective channel
length (L
LD
and L-L
LD
) and threshold voltage (V
tL
and
V
tH
). These calibrations are performed by adjust of the
SPICE parameters in order to reproduce the same
experimental results of the OTAs DC bias and the
frequency response [open-loop voltage gain (A
V0
) and
phase as a function of the frequency (f)] as presented in
figure 1. A good agreement between SPICE simulated
and experimental results has been obtained.
For the noise simulation the parameters of BSIM3SOI
unified flicker (1/f) noise model (NOIMOD=2) [5] of
conventional and GC SOI were adjusted based on
experimental results of ref. [3] (Table II). The
comparison has been made for devices with L=3 µm.
Performing the flicker noise analysis for conventional
and GC SOI nMOSFETs with L
LD
/L=0.33 (L
eff
=2 µm),
both with the same mask channel length, the input-